(1) Field of the Invention
The present invention relates to the field of data interfaces between asynchronously clocked systems. Specifically, the present invention relates to interfaces for the transfer and reception of information between such systems.
(2) Prior Art
A problem encountered with the transmission and reception of valid data between two asynchronous systems is metastability of electronic device signals. The communicated data is truly asynchronous with respect to the receiving clock when it meets two criteria: (1) there is no known phase relationship (one does not know when the signal will change); and (2) there is no known frequency relationship (one does not know how often the signal will change).
Metastability is the act of transitioning into a relatively unstable state of a flip-flop or latch. In this state, the set-up and hold times are violated so that the data input is not a clear one or zero. This causes a finite chance that the flip-flop will not immediately latch a high or a low signal but get impermissibly caught halfway in between. A synchronization failure occurs when the undefined output is sampled by other digital circuitry and propagates through binary systems. A system is not extremely reliable without providing a way to establish the limits of its probability of failure.
Once the flip-flop enters the metastable state, the probability that it will still be metastable some time later has been shown to be an exponentially decreasing function which determines the mean time before failure (MTBF): ##EQU1## Where t' is the metastability settling time, Fc is the clock sampling frequency, To is the propensity for metastability, Fi is the input event frequency and t is the exponential decay rate that indicates how long a device is expected to remain in a metastable state once placed there. It is desired to utilize an interface wherein the MTBF is very high and can be accurately determined within the system. The MTBF is typically increased by decreasing the sampling rate (Fc). Unfortunately, decreasing the sampling rate (Fc) directly increases the latency of data through the synchronizer. It is preferred to maximize the settling time (t') for a given sampling rate. Settling time (t') is the time allowed for a synchronized signal to remain at rest before being evaluated.
Interfacing with data streams which are asynchronous to the VLSI component has always been a problem. Reducing metastability failures without adding latency is becoming more difficult as clock rates continue to increase. For instance, it is desired that parallel processor interconnect synchronization be done in a way that will not reduce data path bandwidth. It is desired to utilize an interface allowing maximum throughput sampling rate.
In the past, several prior art synchronizer designs have been utilized to provide an interface (e.g., integrated within the overall interface electronics) between two asynchronous systems. One such cascaded synchronizer is shown in FIG. 1. This circuit is composed of n+1 cascaded stages (latches 30a-30d) to obtain a delay of approximately n clock cycles of sample clock 35 before the status bit of line 15 is sampled by the receiver system at point 20. Clock 35 is the sampling clock (also called the read clock or receiver clock). Each stage (30a to 30d) provides additional settling time of the status signal 15. During the settling time, a marginal value has the opportunity to resolve to a valid logic level. The amount of settling time desired is selected as a function of the input data and clock frequencies, synchronizer characteristics, and desired MTBF failure rate. Within the circuit of FIG. 1, a synchronized signal will transverse through each synchronizer stage. Propagation delay through each stage reduces the total settling time because the synchronized signal is not at rest during propagation.
The circuit of FIG. 1 specifically shows four serial stages each clocked by signal 35 over line 10. The output data is sampled over line 20. The status bit over line 15 (e.g., from the writing or sending system) is shifted from one stage to the next until it reaches the end. Each stage will add an additional clock cycle of settling time minus the propagation time required for the status bit to pass through the stage. The total settling time for four serial stages is approximately three clock periods minus four propagation delays (one for each stage). For example, at clock frequencies of 200 MHz, and propagation delays of 1 nsec, the total settling time of FIG. 1 is 11 nsecs. Therefore, the four propagation delays reduce the maximum possible settling time by 26% according to: ##EQU2##
FIG. 2 illustrates another prior art synchronizer having a divided sample clock and a single stage. This circuit contains a single stage latch 40a with divided clock enable and provides more settling time per clock cycle over the serial staged synchronizer (FIG. 1) because the synchronized signal has only one propagation delay per n clock cycles, where n is the divided clock parameter (signal 22). The output data is taken (sampled) over line 20 and is input over line 15. The clock signal 35 is divided by three by the latches 40b-40d and used as an enable signal over line 22 to latch 40a. For example, at clock frequencies of 200 MHz and propagation delays of 1 nsec, the total settling time is 9 nsec. This is a 28% improvement over the cascaded synchronizer of FIG. 1. The MTBF of FIG. 2 is expressed as: ##EQU3##
However, the divided clock requires that the asynchronous input stream be sampled with a slower clock frequency than the maximum sample frequency. This reduces the system communication throughput considerably and is undesirable in a parallel processor interconnect. As such, it is desirable to provide an asynchronous interconnect or interface that does not require a divided sampling clock but can rather operate a maximum throughput sampling clock speed.
Synchronizers, such as the above, can be implemented within communication interconnects for providing an interface between two asynchronous systems. In these systems, an empty flag is often generated to indicate that the interconnect (interface) is empty of valid data. Prior art interconnects synchronize both the assertion and deassertion of the empty flag. Serial or cascaded synchronizer stages cannot be reset since pending information is lost in all stages simultaneously. Typical asynchronous interfaces solve the empty flag problem by generating an "almost-empty" flag or signal. The almost-empty signal warns that only a small amount of data resides in the FIFO and reading of the FIFO should be discontinued to prevent reading after the FIFO is empty. The disadvantage to this is that a small amount of data may be left stuck in the FIFO until more data forces deassertion of the almost-empty flag. Throughput is degraded in order to remove the last data from the almost-empty FIFO. It would be desirable to provide a more efficient mechanism for indicating FIFO empty.
Accordingly, it is an object of the present invention to provide an interface between two asynchronous systems. It is further an object of the present invention to provide such interface wherein the interface operates at maximum throughput clock speed and does not require clock dividing. It is yet another object of the present invention to provide such interface that can offer a proportionately large settling time per clock cycle. It is also an object of the present invention to provide such an interface that has a programmable settling time. It is also an object of the present invention to provide a more efficient FIFO empty notification to a receiving system. These and other objects of the present invention not specifically recited above will become clear within discussions of the present invention herein.